1. Field of Invention
This invention relates to an electrostatic discharge protection circuit for metal-oxide semiconductor (MOS) devices in integrated circuit.
2. Description of Related Art
ESD results when electrostatic charge is collected and rapidly discharged in a short duration, high voltage pulse. Such a discharge results from the contacting of a charged object with the integrated circuit. Both equipment and personnel can acquire substantial amounts of electrostatic charge that can subsequently be transferred to an integrated circuit during manufacture or usage. The human body, for example, can generate charges exceeding 2000 V. Static charge is commonly picked up when a person handling the circuit brushes it against a garment. Electrostatic voltages can also originate from poorly grounded equipment and noisy environments. Conventional approaches to the ESD problem have been to provide the protected circuit with devices that can intervene to deflect ESD charges towards the ground.
As integrated circuit devices are made smaller, ESD damage is more likely to occur. MOS devices are particularly sensitive to high voltage discharges due to the liability of rupture of the thin gate oxide. Unfortunately, the performance of ESD protection devices have been negatively impacted by advanced fabrication processes such as lightly doped drain (LDD), silicided diffusion, and thinner oxides. In order to prevent damage to internal circuits, an on-chip ESD circuit, such as the one disclosed by this invention, must be triggerable and able to dissipate built-up power at a voltage substantially below the breakdown voltage for the components on the chip.
Some prior art protection devices include thick field devices (TFD), shown in FIG. 1, and grounded gate thin oxide NMOS (GGNMOS), shown in FIG. 2. Both of these conventional protection devices are based on MOS transistors that operate as NPN bipolar transistor under ESD conditions, where the drain and the source regions act as collector and emitter, respectively, and the base is provided by the region in the substrate between the drain and the source. A graph of I-V characteristic of NPN bipolar transistors is shown in FIG. 3. When voltage reaches trigger voltage Vtri, the NPN bipolar turns on and enters into snapback region of low impedance so as to dissipate high ESD energy. In order to be effective, the protection device must be turned on by a lower voltage (trigger voltage) than the breakdown voltage of the internal circuit. The snapback voltage (Vsp) is also important; the protection device with low snapback voltage can dissipate higher current and achieve higher ESD performance. In general, a good protection circuit must have both low trigger voltage and low snapback voltages.
The higher trigger voltage levels inherent to the conventional TFD and GGNMOS of the prior art render them ineffective power bus ESD protectors; their trigger voltages tend to be too high to protect the weaker internal circuits. Furthermore, advanced processes, such as the salicide process and the use of thinner oxide layers, have further reduced the ESD performance of these prior art devices. Therefore, more and more ESD damage is occurring despite the use of the TFD and GGNMOS approaches.
LDD NMOS itself can be used as a protection device; however, the doped n.sup.- region of an LDD transistor induces non-uniform current distribution and local hot spots, negatively affecting the device's ability to provide protection. As devices shrink in size, the negative effects of local hot spots and non-uniform current distribution become even more pronounced.
Devices also exist in the art in which an LDD NMOS device is coupled with a RC circuit, as shown in FIG. 5. However, the non-uniformity of current distribution inherent in an LDD device cannot be completely resolved with the coupling of a RC circuit.
In order to avoid the problems produced by the LDD regions, non-LDD devices of prior art have also been used to provide ESD protection. An example of a non-LDD NMOS without the n- implant is shown in FIG. 4. The absence of n- doped regions in such devices avoid completely the problems of non-uniform current distribution and local hot spots, both of which negatively impact the ESD performance of LDD devices. Still, the trigger voltages of such devices are not low enough to prevent internal circuit damage in some settings.
The NMOS devices with salicide (self-aligned silicide) processes of prior art, shown in FIG. 6, have similarly been used to provide ESD protection. However, they generally have low ESD performance due to the small spacing (DS) between contact and gate/diffusion. When the silicide on the conducting contact is very close to the junction edge, as occurs in salicide processes, a current concentration occurs, serving as a source of heat in an ESD event. Consequently, the silicide melts or agglomerates in an ESD event, causing a failure. In order to avoid this problem, silicide blocking mask of prior art is used to increase the distance between contact and gate/diffusion, shown in FIG. 7
Accordingly, it is desirable to provide improved ESD protection circuits.